A view into the world of building chips: Design Automation Conference (DAC), June 2017

DAC2017

DAC2017

S3semi exhibited this year at the Design Automation Conference in Austin, Texas. This has historically been a conference focused on the latest developments in how to design chips. Originally the key participants were from the Electronic Design Automation (EDA) sector, however a number of years ago, the remit extended to include silicon IP vendors, largely because the channels to market for both EDA and IP companies were the same. In addition, the various pure-play semiconductor foundries exhibit and historically some ASIC design houses have also exhibited. The foot-fall this year at DAC was significantly smaller than prior years. This was largely due to its location, as the local semiconductor industry catchment area is limited to perhaps 4-5 semiconductor companies. Next year DAC will move back to the Mascone Centre in San Francisco, which is expected to achieve greater participation due to its proximity to Silicon Valley. Included here are a number of observations from the show

EDA: Business as usual

DAC was as usual dominated by the big 3 EDA tool vendors, those being Cadence, Synopsys and Mentor Graphics. The usual set of specialist EDA vendors were also exhibiting covering specialist functions ranging from digital backend and frontend, analog simulation and automation (a challenge that has yet to be cracked in a robust manner) to board-level and FPGA design optimization tools. Key EDA themes this year were around how to manage designs in the latest foundry FinFet process nodes (typically <16nm process geometries).

Semiconductor foundries: Samsung put on quite the splash

Samsung was the most notable semiconductor foundry to exhibit at DAC, followed by SMIC and then TSMC. Global Foundries and UMC were not present.  Tower Jazz had a presence, along with AMS. In short, there was a good mix of those foundries promoting their FinFet roadmap (Samsung) in addition to those promoting their More-than-Moore process roadmaps (SMIC, TJ & AMS).  However, from an eco-system enablement perspective, TSMC continues to exhibit the greatest breadth across all process nodes

Silicon IP: Business as usual

As usual, there was a rich mix of IP vendors at the show, covering all functions from high-speed serdes, processors, security and analog IP right through to specialist IO and verification IP.  The show does provide a good opportunity to interact with domain experts in each of these areas. In fact,  S3semi gave a short talk at DAC, on its high-efficiency ADC IP portfolio targeting both broadband and narrow-band communication channels. See here:

https://youtu.be/eJoIpfyxsuU

Navigating the Chip design complexity

At S3semi we have been building chips for over 20 years. We understand how to navigate the complex eco-system of the chip design industry, and more importantly how to get the best out of each element, whether that be EDA tools, 3rd party IP, semiconductor foundry selection, or test and packaging house selection, and logistics. We are experts at supporting customers who do not necessarily have chip design expertise, but who need a dedicated custom chip of their own, be it in a mid or low volume application space.

Want to know more about how to build that custom integrated chip?  Contact us at info@s3semi.com

2018-04-06T06:54:35+00:00 June 28th, 2017|Blog|

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