SAN JOSE, Calif., Jan. 30, 2007 – Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced that Silicon & Software Systems Ltd. (S3) achieved record-breaking production success for a chip designed at S3’s facilities, using the company’s nanoflowLP® low-power system-on-chip (SoC) design flow based on the Cadence® Low-Power Solution.
S3 used a range of low-power design techniques such as multi-Vt libraries, power islands, power estimation and low-power verification for this chip, intended for mobile audio applications. The chip booted correctly the first time in a portable computer application within 24 hours of wafers arriving from the foundry and consumed only 85 percent power of the original power budget target set by the customer.
The Cadence Low-Power Solution integrates leading-edge design, verification, and implementation technology with the Si2 Common Power Format (CPF), a standardized format for specifying power-saving techniques early in the design process, to deliver an end-to-end low-power design solution to IC engineers. By preserving low-power design intent throughout the design, the solution eliminates laborious manual work, greatly reduces power-related chip failure, and provides power predictability early in the design process. This holistic approach to addressing the low-power challenge is necessary for managing power consumption in 90-nanometer and 65-nanometer designs.
“With the Cadence Low-Power Solution we were able to optimize our nanoflowLP and leverage our strong engineering expertise and experience,” said Dermot Barry, general manager, System IC Business Unit, S3. “As a result, our customers achieve right-first-time silicon and reduced time to revenue. With the latest low-power optimized flow from Cadence we can now meet the high expectations of our customers.”
“We applaud S3’s ability to deliver another customer success based on our extensive low-power flow-development partnership. The exciting technology advancement by the Cadence Low-Power Solution, based on the Common Power Format, brings a new level of automation to the ever challenging low-power designs at deep sub-micron nodes,” said Dr. Chi-Ping Hsu, corporate vice president, IC Digital and Power Forward at Cadence. “S3’s ability to incorporate the latest low-power techniques and deliver fast turn-around times means that lowest cost SoCs can be achieved with minimal risk or compromise on performance.”
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available atwww.cadence.com.
About Silicon & Software Systems Ltd.
S3 is a consumer electronics design company focused on the home entertainment, mobile multimedia and consumer healthcare markets. The company designs integrated circuits and embedded software solutions for its worldwide client base. S3’s comprehensive portfolio of mixed-signal IP and design solutions delivers power-efficient single chip systems for clients developing SoCs at the 90-nanaometer and 65-nanometer technology nodes. S3’s clients achieve accelerated time-to-revenue and reduced design risk, benefiting from over twenty years of successful, leading-edge IC development. For further information please visitwww.s3group.com.
Andrea Huse, Sr PR Manager, EMEA
Cadence Design Systems, GmbH
Direct: +49 89 (0) 4563 1726
Cadence Design Systems, Inc.
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